As the processing speed of microprocessors increases, the demand for memory devices having faster access times also increases. Memory system designers have developed methods and designs that shave off nanoseconds from access times in order to satisfy the demand for high speed memory devices while operating under low voltage conditions. Even with the advances made in memory device designs, the fundamental building blocks of memory devices have remained relatively the same. As will be described in more detail below, these building blocks are the basic elements that are shared among all types of memory devices, regardless of whether they are synchronous or asynchronous, random-access or read-only, or static or dynamic.
A conventional memory device is illustrated in FIG. 1. The memory device includes an address register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory bank arrays 20 and 22 depending upon the state of a bank address bit forming part of the row address. The arrays 20 and 22 are comprised of memory cells arranged in rows and columns. Associated with each of the arrays 20 and 22 is a respective row address latch 26, which stores the row address, and a row decoder 28, which applies various signals to its respective array 20 or 22 as a function of the stored row address.
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. The column address latch 40 momentarily stores the column address while it is provided to the column address buffer 44. The column address buffer 44 applies a column address to a column decoder 48, which applies various column signals to respective sense amplifiers and associated column circuits 50 and 52 for the respective arrays 20 and 22. Data to be read from one of the arrays 20 or 22 are coupled from the arrays 20 or 22, respectively, to a data bus 58 through the column circuit 50 or 52, respectively, and a read data path that includes a data output buffer 56. Data to be written to one of the arrays 20 or 22 are coupled from the data bus 58 through a write data path, including a data input buffer 60, to one of the column circuits 50 or 52 where they are transferred to one of the arrays 20 or 22, respectively. The read data path and the write data path generally represent a data path of the memory device 10.
The above-described operation of the memory device 10 is controlled by a command decoder 68 responsive to high level command signals received on a control bus 70. These high level command signals, which are typically generated by the memory controller, are a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, where the “*” designates the signal as active low. The command decoder 68 generates a sequence of command signals responsive to the high level command signals to carry out a function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
As mentioned above, read data are coupled from one of the arrays 20 and 22 to the data output buffer 56 and the data bus 58 through a read data path that is shown in greater detail in FIG. 2. FIG. 2 illustrates a conventional data path 200 for a memory device. The data path 200 includes a plurality of local input/output (LIO) lines 204, 208, 212 coupled to a global input/output (GIO) line 220. The LIO lines 204, 208, 212 are represented by a pair of signal lines that are coupled to a respective signal line of the GIO through respective pairs of NMOS pass gates 224a, 224b, 224c. Coupled to the LIO lines 204, 208, 212 are respective LIO precharge circuits 240 to precharge the LIO lines 204, 208, 212 to an internal voltage level VINT. A GIO precharge circuit 244 is coupled to the GIO line 220 to precharge the GIO line 220 to the VINT voltage level as well. A global sense amplifier 250 is coupled to the GIO line 220 to sense a voltage or current difference between the GIO signal lines 220a, 220b and in response generate an output signal that is provided to the output buffer 56 (FIG. 1).
Each of the LIO lines 204, 208, 212 is further coupled to either of the memory arrays 20, 22 through sense amplifiers 50, 52, all respectively. As shown in FIG. 2, the LIO lines 204, 208, 212 are coupled to the memory array 20 and sense amplifiers 50. The memory array 20 and sense amplifiers 50 previously described with respect to FIG. 1 are segmented such that a segment is associated with a respective one of the LIO lines 204, 208, 212. Each of the columns of memory cells of the memory cell array 20 is represented by a pair of digit lines (not shown) coupled to a respective one of the sense amplifiers 50. As known in the art, when the memory cell array 20 is accessed, a row of memory cells (not shown) are activated, and the sense amplifiers 50 amplify data for the respective column by coupling each of the digit lines of the selected column to a voltage supply or ground so that the digit lines have a complementary logic levels.
In operation, when a memory cell is read, a selected pair of digit lines of a column of memory is coupled to the LIO line 204, 208, 212 associated with the memory cell being accessed based on a column address provided to the memory device. Selection of a the column of memory coupled to the LIO line 204, 208, 212 is made by a common column decoder (not shown) coupled to the sense amplifiers 50a–50c. As known, in normal operation only one of the LIO lines 204, 208, 212 is coupled to the GIO line 220 through the respective NMOS passgates 224 during the read operation. By coupling the particular LIO line to the GIO line 220, a potential difference is created in the pairs of GIO signal lines 220a, 220b. The potential difference is detected by the GIO sense amplifier 250, and in response, an output signal is generated to be provided to the output buffer 56 (FIG. 1).
Typically, the GIO lines 140 are physically long signal lines that are routed over the memory device and are selectively coupled through the physically shorter LIO lines to a respective current sense amplifier 50. Due to its length, the GIO lines 220 have considerable line impedance that can significantly increase the time for sensing read data from the memory cell array 20 when voltage mode sensing is used since the sense amplifier coupled to the LIO line will need to drive the signal lines of the GIO lines 220 to complementary levels. Similarly, when data is written to a memory cell, the line impedance will also negatively affect the write time. That is, to write the data to the memory cell, the GIO signal lines 220a, 220b are driven to the appropriate voltage levels representative of the data to be written and its complement by the GIO sense amplifier 250 in order to set the selected sense amplifier (not shown) coupled to the LIO signal lines, either 204, 208, or 212, depending on which memory array 20a, 20b, or 20c to which the data is being written, to the appropriate voltage levels to write the data. As known in the art, the speed at which a sense amplifier is set to the appropriate voltage levels is based on the time to drive one input/output node of the sense amplifier to ground. With the physically long GIO lines 220a, 220b precharged to the VINT voltage level, the amount of time to transition the LIO signal lines from the VINT voltage level to ground can be prohibitive.
As well known, the memory cells of a memory device are tested for functionality, with defective memory cells being repaired through the use of redundant memory. As memory densities have increased, the time for testing the functionality of all of the memory cells of the memory device has also increased. Various circuits for test compression have been designed into the memory devices as an approach to alleviate this problem. Typically, a test mode is invoked, and the functionality of multiple memory cells are tested concurrently by reading the data from the multiple memory cells and “compressing” the data through logic circuitry to produce a single flag having a logic state that is indicative of whether the data from any of the multiple memory cells do not match the data that is expected. Thus, rather than reading data from each memory cell individually, groups of memory cells can be tested concurrently with the flag indicating whether any of the multiple memory cells is defective.
As shown in FIG. 2, the conventional data path 200 cannot perform test compression for multiple cells located in the memory arrays 20a–c. In the event of an error, the GIO signal lines 220a, 220b would have an unknown voltage due to the coupling of the GIO signal lines 220a, 220b to different voltages through the LIO signal lines coupled to the defective memory cell and through the LIO signal lines coupled to the functional memory cells. For example, assuming that the memory cells located in the memory arrays 20a, 20b are functional, and the memory cell located in the memory array 20c is defective, the complementary voltages of the LIO signal lines 212a, 212b are opposite of the complementary voltages of the LIO signal lines 204a, 204b and 208a, 208b. Consequently, when the NMOS passgates 224a–c are activated to couple the LIO lines 204, 208, 212 to the GIO line 220, the different complementary voltages of the respective LIO signal lines will cause the voltage of the GIO signal lines 220a, 220b to be neither ground nor VINT. Thus, the GIO sense amplifier will not be able to determine from the unknown voltage levels of the GIO signal lines 220a, 220b what output signal to generate.
Therefore, there is a need for a data path that facilitates high speed memory operations and that can be used to provide test compression functionality.